Is the breakthrough here about emission or transmission? Or is the physics for these two connected? It's not clear to me, between the title and the article.
Secondly, could using a "photonic" memory bus bring RAM access speeds close to cache speeds, or is the transmission distance/time not the main issue there?
They were able to measure a strong photoluminescence signal from the silicon germanium nanowires. Photoluminescence is a good proxy for how efficiently it will light up - carriers are generated optically with a light source more energetic than the bandgap of the material. This is much easier than fabricating a full device with electrical contacts.
Silicon is typically a really lousy photon emitter because it’s an indirect bandgap material. Turning an electron/hole pair into a photon requires an interaction with a phonon. It seems by getting the silicon to grow in a hexagonal orientation, it becomes a direct bandgap material leading to much higher emission efficiency.
> Secondly, could using a "photonic" memory bus bring RAM access speeds close to cache speeds [...]
No, it really can't. The distance between CPU core and DRAM chips is approximately 10 cm, so at a typical electrical propagation speed of around 2/3 c, the round-trip time is 1 ns. A full DRAM access, however, is on the order of 100 ns. So physical transmission speed only accounts for about 1% of DRAM access times.
The speed is not limited by propagation delay, but by signal integrity. It is non trivial to have an external parallel bus operating at low Ghz speed. On chip signals can be much faster because they don’t have the capacitive load.
On top of that is power requirements which are again orders of magnitude higher than on chip signals.
Optical has a chance to fix that for the same reasons it works so well for longer distance networking.
What you're saying applies to throughput, not latency.
> On chip signals can be much faster because they don’t have the capacitive load.
You can routinely achieve > 30 Gb/s off-chip in copper cables over distances > 1 m using differential signaling [1]. Capacitive load is only a limiting factor if you directly drive the gate of a transistor.
[1] For example, high-end Xilinx FPGAs provide several of those transceivers. They really operate at > 30 GHz.
True it won't affect latency. Yet caches are pretty good at ensuring most DRAM requests take advantage of the hardware parallelization available.
That’s why despite DRAM having pretty much constant latency for the last 20 years bus speeds and bank counts have been consistently increasing. Optical interconnects will help immensely.
We may also see things like off chip SRAM come back into vogue once its feasible to take advantage of their performance.
Transmission time isn’t really the main issue, it’s more about the work required to get a memory request through the levels of the hierarchy to DRAM and back. Probing each level of cache, propagating through the miss queues, translation (maybe with TLB miss), waiting for the DRAM controller, etc.
What? That doesn't make sense. If cache probing would be the cause for DRAM accesses being slow, we wouldn't need caches. We would just access DRAM directly!
It's the other way around: DRAM accesses are slow, that's why we need caches.
> translation (maybe with TLB miss)
In most architectures, the caches are physically addressed, so TLB lookups occur before even L1 cache access. Successful TLB lookups are extremely fast! And you can't skip the TLB, even if you don't have any data caches.
I wasn’t suggesting probing caches is the main cost, I only wanted to describe that there is a long journey to DRAM in current architectures of which signal propagation is such a small part.
You are totally right that if you can make the resultant communication speed faster you could theoretically do away with caches. However this approach wouldn’t solve that problem on its own. Also forget not that cache is expensive and DRAM is cheap!
Yes I’m aware that caches can be physically addressed and you could reorder the sequence I described. No you can’t skip the TLB, but a hit will be faster since you don’t have to perform translation.
> In most architectures, the caches are physically addressed, so TLB lookups occur before even L1 cache access.
So to see if a memory location is contained in a cache line, a TLB lookup is needed to first get the physical address? I wouldn't have expected this, can you expand on why this is the case?
Two reasons: 1) a virtual address might refer to different physical addresses (see pwildani's comment), and 2) a physical address can be mapped to different virtual addresses – a virtually addresses cache has to keep track of that somehow, otherwise the cache will become incoherent.
Interesting - if that's the case I would imagine it make sense for some systems to feature an architecture which skips the idea of multilevel cache entirely and has only RAM connected over a photonic bus. No probing, no cache misses.
Secondly, could using a "photonic" memory bus bring RAM access speeds close to cache speeds, or is the transmission distance/time not the main issue there?